1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which performs a clock-synchronized read-modify-write (RMW) at high speed.
2. Description of the Prior Art
A synchronous semiconductor memory has been promoted for high speed input/output interface. This memory device, however, has a problem in not so high speed of the read-modify-write (RMW) which is important for graphic use. The read-modify-write (RMW) is such a function that after data have been read out from the memory, a graphics controller or a CPU modifies and corrects for subsequent rewriting operation of the modified and corrected data. The read-modify-write (RMW) is used for the purposes of reversing the color, blinking the pattern of image, both on a CRT display, and so on.
FIG. 1 is a circuit diagram illustrative of a conventional synchronous semiconductor memory. In FIG. 1, a circuitry has a flip-flop 1 which latches address signals synchronizing with set-up timing of a first clock CLK. These address signals are inputted to an address decoding circuit 2 for decoding the address signals. The decoded address signals are then inputted to a latch circuit 3 which latches the signals at timing of a second clock CLK2. The latch circuit 3 outputs column selecting signals YSWs.
On the contrary, control signals such as RAS, CAS, WE, etc. are decoded in a decoding circuit 11, where RAS means row address strobe signal, CAS means column address strobe signal, and We means for write enable signal. The signals outputted from the decoding circuit 11 are thereafter latched with a read command circuit 12 and with a write command circuit 13 at timing of a delayed first clock CLK which has been delayed by a time for decoding the signals in a delay circuit 16.
Upon input of a read command supplied from the read command circuit 12, the read control circuit 14 makes a read amplifier 7 amplify the data outputted from a sensing amplifier 6 selected by the column selecting signals YSWs. The data amplified with the read amplifier 7 is outputted to an input/output pin DQ at set-up timing of a third clock CLK3 outputted from the read control circuit 14. At the same time, for stopping a write command a signal has inputted to a write control circuit 15.
In a write operation, a write control circuit 15 controls a write amplifier 9 and a write switch (WSW) for write-operation of data inputted by an input buffer 10 when the first clock CLK is risen. At this time, a signal has been inputted to the read control circuit 14 to stop a read command.
The above description was made assuming that in the above mentioned read and write operation, a memory cell 5 holds data on a word line selected with a row decoder 4, where the data have been amplified by the sensing amplifier 6, similarly to that of the conventional DRAMs.
FIG. 2 is a timing chart illustrative of operations the conventional synchronous semiconductor memory as shown in FIG. 1. In FIG. 2, the read and write command are inputted at set-up timing of the first clock CLK. A read command (RCMD) is inputted at the timing of the clock No.1. After the read command has been inputted, data are read out at the set-up timing of a column selecting signal (YSW), similarly to that of conventional DRAMs.
The read out data are then outputted as the read-data RD1 at the timing of the clock No.3. The time duration defined between the clock No.1 and the clock No.3 means that the CAS latency equals three (CL=3) as shown in FIG. 2. The current technology demands operation at CL=3 under condition of 100 M Hz frequency, or 10 nsec clock cycle. If, however, the CAS latency is set at one, or CL=1, then the maximum operation frequency will be 33 Mhz. This low operation frequency causes a poor performance of the memory device. It is, therefore, the best choice that the CAS latency is set at three (CL=3) as shown in FIG. 2.
The read-data RD1 is supplied into the controller such as a graphics controller, a CPU, etc. at the timing of the clock No.4 for rewriting the same after modified and corrected. This rewrite process is made at the timing of the clock No.6 because the clock No.6 is the earliest timing capable of inputting the write command. Not withstanding, the clock No.5 is not suitable for the above purpose because of the necessity for setting the data bus in a high impedance state. This high impedance state of the data bus is set to avoid a collision between the memory driving signal and an external controller driving signal.
The memory stops driving the data bus for entry into the high impedance state after a predetermined time period has been passed from the clock No.4. If data writing is made at the timing of the clock No. 5, the controller has to drive the data bus before the clock No.5, because it is necessary to input a command and data for satisfying the setup time before the clock No. 5 is risen.
Actually, the above mentioned operation of stopping to drive the data bus is made in accordance with the specification of the memory device.
A data writing is made by a command inputted at the timing of the clock No.6. Namely this data writing is made during the time period when the column selecting signal (YSW) is set up and the write-switch signal (WSW) is in the HIGH level. Data are supplied through the data bus into the memory for a read-modify-write (RMW) operation, and the input of the next read command will be enabled at the timing of the clock No.7.
In the above mentioned synchronous semiconductor memory, a data bus commonly serves for both data writing and data reading. As a result, it is necessary to have the read command and the write command function exclusively to each other. Also it is necessary that the read command is inputted at the timing of the clock No.1, and data are supplied into an external controller, then the modified data are written at the timing of the clock No.6. Further it is necessary to conduct the next reading at the timing of the clock No.7.
As mentioned above, the conventional synchronous semiconductor memory has the synchronous interface which enables continuous reading and writing at higher speed than the normal DRAMs. However, a read-modify-write (RMW) speed is almost the same as the normal DRAMs. Namely, in a high speed page mode, the normal DRAM can conduct the read-modify-write (RMW), for example, in 60 nsec because of its capability of 30 nsec cycle read/write operation. The conventional synchronous semiconductor memory, however, needs 60 nsec for the read-modify-write (RMW), which is the same time as the normal DRAM, in spite of 10 nsec cycle operation.
The performance of the conventional synchronous semiconductor memory is the same as the normal DRAM which is operable in a high speed page mode. That is why the conventional synchronous semiconductor memory needs one dummy clock to avoid a signal collision in the data bus at the time of changing from read operation to write operation, even pipe-line operation is made for high speed clock cycle.
To speed up a read-modify-write (RMW) was proposed in the Japanese Laid-open Patent Publication No.61-104391. The proposed technique is implemented by forming a circuitry which comprises the normal DRAM circuit and is a shift-register circuit operating in a synchronous with the former one. Since, however, only this circuitry cannot operate a read-modify-write (RMW) to a voluntary column address, the document proposes adding some circuits as shown in FIG. 3. In the circuitry shown in FIG. 3, a shift-register column 21 is provided through a transfer-gate column 20 connected to bit-line BL1-BL256 connected to columns 1-256. The shift-register column 21 outputs signals to a output-gate column 22. The drains of the transistors as elements of the output-gate column 22 are connected to a data bus DB. This data bus DB is connected to a modification circuit 25.
The technique proposed in the document can increase the speed of a read-modify-write (RMW) operation. However, the prior art needs shift-registers in addition to the memory cells of the normal DRAMs as mentioned above. Consequently, the prior art merely provides the memory device like the conventional VRAM which consists of a dual-port-memory. As a result, it is led to a problems in increase of the memory-chip-size and in a high manufacturing cost.